View MN1959041_223796.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Communication Equipment LSI
MN1959041
Commercial MPEG-4 Video Codec IC for W-CDMA Mobile Visual Terminals
s Overview
MN1959041 is an image-processing DSP that adopts a vector pipelined architecture. It provides an extensive set of features that allow it to implement the high-efficiency image and video encoding and decoding required for image communication, recording, and playback. It implements encoding and decoding that conform to the H.263 and MPEG4 Simple@L1 video encoding standards, and decoding that conforms to the MPEG-4 Simple@L3 video encoding standard. It includes dedicated special-purpose circuits for high-speed decoding of the MPEG-4 core profile.
s Features
* General-purpose DSP core (MP: Main Processor) that can implement complex processing flexibly * Provides an instruction set of 43 instructions, including both scalar and vector instructions. * Provides interrupt control and task management functions that issue VCE/VIF/MIF (described later) start/stop instructions and DMA transfer instructions. * Special-purpose arithmetic circuit (VCE: Video Codec Engine) that implements a high-speed video codec * Integer precision and half-pel precision motion detection circuit (MEF/MEH) * Discrete cosine transformation/inverse discrete cosine transformation circuits (DCT/IDCT) * Variable-length encoding and decoding circuits (VLC/VLD) * Blocking noise elimination circuit (PNR) * Shape information decoding circuit (CAD) * Pixel supplementing circuit (PADDING) * Image synthesis circuit (COMPOSITE) * Full complement of image signal input and output functions * Video interface circuit (VIF) that supports both portrait and landscape orientation LCDs * Support for CIF and QCIF 4:2:2 format video input from CMOS cameras * P in P function that displays a subscreen in the lower right of the main screen * Cursor and blue background display functions. * Mosquito noise elimination filter * Functions for picture quality adjustment and for combining video and graphics * IIC (Inter IC) interface (Conforms to Version 2.0, standard and fast mode) * Video signal format conversion function (YCbCr 4:2:2 RGB; can be stopped when not needed.) * Graphics overlay function (Either post RGB conversion or post dithering can be selected.) * Video signal adjustment functions: outline enhancement, tint, color gain, brightness, contrast, and gamma adjustment * Dithering function for pseudo 24-bit color (2 x 2 matrix) * Monochrome conversion function (Either monochrome or sepia can be specified.) * Allows moving the display area (a 176-pixel x 220-line area placed anywhere within a 352-pixel x 288-line image) * YCbCr 4:2:2 test image generation function (75% color bar, horizontal/vertical stripe, arbitrary brightness/color difference) * Camera reset control function * Large on-chip DRAM capacity * On-chip 20 Mbit DRAM provided to reduce parts counts and achieve overall system cost reductions
Publication date: November 2002
SDM00008AEM
1
MN1959041
s Features (continued)
* Built-in multifunction memory interface * Memory interface circuit (MIF) for batch centralized management of DMA transfers between internal DRAM and the following internal circuit blocks: main processor (MP) block, host interface (HIF) block, and video interface block (VIF). * 16-bit internal DRAM bus width for high-speed data transfers * Adopts a DMA transfer reservation and reservation unit prioritization method for efficient data transfers. * Ring buffer structure and matrix address access structure * Extensive set of peripheral functions * One nonmaskable and two maskable interrupt systems * Parallel I/O functions * Timer functions * Microcode downloading function * Program debugging mode * Provides a dedicated debugging mode that can access all memory spaces in the IC for easy program debugging during microcode development. * Supply voltage: 3.3 V external (2.9 V) and 1.8 V internal PLL block: 3.3 V (2.9 V) DRAM block: 3.3 V and 1.8 V * Internal operating frequency: 54 MHz (External input frequency: 76.8 kHz) * Package: 239-pin CSP
s Applications
* Cell phones, PDAs, and other communication equipment
2
SDM00008AEM
MN1959041
s Block Diagram
MN1959041 consists of the following hardware blocks. * MP (Main Processor) * IRC (Interrupt Controller) * HIF (Host Interface) * VCE (Video Codec Engine) * MIF (Memory Interface) * VIF (Video Interface) * Visual ASIC * DBC (Debug Controller)
VCE ME Local Memory VLC Local Memory VLD Local Memory PNR Padding Local Memory CAD Local Memory Composite
DCT/ IDCT
MP DBC MP Core Instruction Memory Data Memory IRC HIF CPU
MIF VIF DRAM (2M-bit) Main Filter Sub Graphics DRAM (2M-bit) DRAM (16M-bit)
Visual ASIC
Video Input
Video Output
SDM00008AEM
3
MN1959041
s Functional Description
1. MP (Main Processor) Block The MP block is a processor core that can interpret and execute programs. It has the following features. * 16-bit fixed-point DSP core * Instruction cycle: 18.6 ns (53.76 MHz) * Most instructions execute in a single machine cycle. * Instruction length: 32 bits, data length: 16 bits * Program memory: 16K words, boot memory: 1K words * On-chip data memory: total of 21K words in three areas * Data path functions: 16-bit extended arithmetic and logic unit (EALU) Multiplier: 16-bit x 16-bit Arithmetic unit: 32 bits Shifter: 32 bits General-purpose registers: sixteen 16-bit registers * Double bank data memory structure that supports parallel execution of DMA transfers and MP internal calculations * Each data memory has its own matrix addressing generator for accessing matrices in a memory space. * Provides vector pipelined arithmetic instructions that allow a single engine block to be embedded in a vector pipeline for execution. * Conditional vector pipeline instructions * Loop control with four independent loop counters * Subroutine control with up to 16 levels of nesting * Dedicated interrupt program counter stack 2. IRC (Interrupt Controller) Block MN1959041 can temporarily halt an executing program when an interrupt request occurs, transfer control to an interrupt handler, and then continue the interrupted program when the interrupt handling completes. This interrupt function does not interrupt instruction execution itself, but occurs between instructions. Note that this means that when an instruction that requires multiple clock cycles, such as a vector instruction, is executing, there are periods when interrupts cannot be accepted. Also note that there are cases where the occurrence of an interrupt can result in an MP or VCE state transition. There are two types of interrupt: internal interrupts that occur within the MP, and external interrupts that occur outside the MP. Interrupts also are classified into the following two classes: Maskable interrupts: interrupts that can be enabled or disabled under program control, and Nonmaskable interrupts: Interrupts that cannot be disabled. Interrupts are assigned priority levels, and when multiple interrupts occur at the same time, the interrupt with the highest priority is accepted first. When multiple interrupts with the same priority level occur at the same time, either the software must determine the priority level or the priority must be controlled in software using the interrupt mask register. Table 1 shows the interrupt types.
4
SDM00008AEM
MN1959041
s Functional Description (continued)
2. IRC (Interrupt Controller) Block (continued) Table 1. Interrupt Types Priority level 1 2 3 Masking Interrupt Watchdog timer interrupt External pin nonmaskable interrupt Stack exception (stack overflow) Stack exception (stack underflow) Software interrupt Interrupt request No. 0 * * * Interrupt request No. 12
High Nonmaskable Nonmaskable Maskable Maskable Maskable Maskable Low
3. HIF (Host Interface) Block The HIF block performs the data transfers between MN1959041 and an external CPU. The IC and the CPU are connected by a 16-bit data bus. During these transfers, the CPU must set, in advance, the bus mode, which determines the physical usage of the data bus. The CPU must set up 16-bit bus mode for transfers with the IC, but can use 8-bit or 16-bit access for other purposes. For example, the CPU can use 8-bit access for bit stream data, and use 16-bit access for all other data transfers. A total of 32 signal lines are required for to the host memory (HM), and for write operations, the IC uses two write enable lines to distinguish between 8-bit and 16-bit access. For read access, the IC always operates in 16-bit output mode in response to the read enable signal. (The CPU must distinguish between the 16 bits of valid data and 8 bits of valid data cases.) 4. VCE (Video Coded Engine) Block MN1959041 includes a built-in VCE that executes video codec operations at high speeds. In particular, it includes the following circuits. * Motion detection circuits (MEF, MEH) * Discrete cosine transformation/inverse discrete cosine transformation circuits (DCT/IDCT) * Variable-length encoding and decoding circuits (VLC/VLD) * Blocking noise elimination circuit (PNR) * Shape information decoding circuit (CAD) * Pixel supplementing circuit (PADDING) * Image synthesis circuit (COMPOSITE) The tables below shows the special-purpose circuits (engines) that form the VCE classified as encoder engine or decoder engine. Table 2. Encoder Engines Engine MEF MEH VLC DCT/IDCT Function Full pel motion detection Half pel motion detection Variable-length coding One-dimensional DCT/IDCT calculation Type A A A B
SDM00008AEM
5
MN1959041
s Functional Description (continued)
4. VCE (Video Coded Engine) Block (continued) Table 3. Decoder Engines Engine MEH IDCT VLD PNR PADDING CAD Half pel generation One-dimensional IDCT calculation Variable-length decoding Blocking noise elimination Horizontal/vertical, expanded, and fixed-value padding Shape information decoding Function Type A B A B A A B B
COMPOSITE Image composition THROUGH Data through (Data is output without processing)
The CAD, PADDING, and COMPOSITE items in the above table are core profile engines. The engines in the VCE block are classified into type A and type B engines. Type A engines operate independently of the MP block, and type B engines operate in conjunction with the MP block. 5. MIF (Memory Interface) Block The MIF block arbitrates and controls DMA transfers between the MP, HIF, and VIF functional blocks. The following are the main types of DMA transfers provided. * Data transfers with the MP DM (Data Memory). These are used for functions such as motion detection and compensation. * Data transfers with the HIF HM (HIF Memory). These are used for bit stream data. * Image data I/O transfers with VIF performed at fixed periods. Requests for DMA transfers other than video I/O are issued with priorities assigned from the MP. Although VIF DMA transfers are performed with the highest priority (level 0), the transfer priority for other DMA transfers can be specified. Table 4 lists the types of priority level. Table 4. Priority Level Types Level Level 0 Level 1 Level 2 Level 3 Low Priority High Usage Only used for image I/O Programmable
The MIF supports the four addressing modes listed below. 1) P+ 2) Sag+ : Consecutive access : Matrix access
3) RP+ : Ring buffer access 4) RP+DF : Ring buffer access with start address offset (every transfer) MN1959041 provides two large-capacity DRAMs; working memory and frame memory. Working memory is mainly used for image compression and expansion, and frame memory is mainly used as the frame buffer used for VIF image output. Working memory is 16 Mbits of DRAM formed from four 4 Mbit DRAMs. Frame memory consists of a video buffer and a graphics buffer, each of which formed from a single 2 Mbit DRAM for a total of 2 DRAM chip. The operation frequency used is 53.76 MHz. Table 5 lists the internal DRAM structures and details of these memories. 6
SDM00008AEM
MN1959041
s Functional Description (continued)
5. MIF (Memory Interface) Block (continued) Table 5. Internal DRAM Structure Work Memory Capacity Bus width Transfer speed Use 16M-bit (4M-bit x 4) 16-bit 53.76 MHz Used by the MP. Frame Memory 2 M-bit x 2 64-bit 53.76 MHz Used by the VIF for video and graphics.
6. VIF (Video Interface) Block MN1959041 includes the VIF block as the interface that passes image data between the IC and the image sensor and the LCD display. The VIF input system provides functions for acquiring, at the stipulated frame rate, CIF or QCIF images sent from an external image sensor at 15 fps, and storing those images in working memory (internal DRAM) as object images for encoding. The VIF output system provides functions for output of images encoded internally in the IC for LCD display at 60 fps. It also provides image size conversion from QCIF to CIF, mosquito noise elimination filter execution as required for QCIF images, functions for subscreen generation and display at lower right of the main screen, and a cursor display function. In the VIF block, video images are processed in YCbCr format, and graphics images are processed in RGB format. The VIF block supports two screen display modes. The first is a full-screen mode that displays all of the image data in the CIF size on the LCD, and the other is a window display mode in which an arbitrary part (176 x 220) of the CIF size output from the VIF is displayed on the LCD. Actual output to the LCD is performed through the Visual ASIC block. 7. Visual ASIC Block The Visual ASIC block takes the video and graphics data output from the VIF block as input, synthesizes the final images, and adjusts the image. The features of the Visual ASIC block are listed below. * IIC (Inter IC) interface (Conforms to Version 2.0, standard and fast mode) * Video signal format conversion function (YCbCr 4:2:2 RGB, can be stopped when not needed.) * Graphics overlay function (Either post RGB conversion or post dithering can be selected.) * Video signal adjustment functions: outline enhancement, tint, color gain, brightness, contrast, and gamma adjustment * Dithering function for pseudo 24-bit color (2 x 2 matrix) * Monochrome conversion function (Either monochrome or sepia can be specified.) * Allows moving the display area (a 176-pixel x 220-line area placed anywhere within a 352-pixel x 288-line image) * Provides a 4-format LCD connection interface. * YCbCr 4:2:2 test image generation function (75% color bar, horizontal/vertical stripe, arbitrary brightness/color difference) * Camera reset control function
SDM00008AEM
7
MN1959041
s Functional Description (continued)
8. DBC (Debug Controller) Block MN1959041 provides its own debugging mode functions, and, when it is in HOLD mode, provides functions for reading and writing internal registers and memory, setting MP breakpoints, and other debugging operations. These functions can contribute to improved efficiency when debugging actual end products, and improved efficiency in system debugging. The IC provides the following functions in debug mode. * Read and write operation to internal registers * Read and write operation to internal memory spaces * Read and write operation to internal DRAM * Breakpoint setting functions PC value break DM1 address break DM2 address break GM address break CM address break * PC trace function 1-bit trace 7-bit trace 9. Operating States and State Transition Control MN1959041 has 4 operating states: RUN, HOLD, SLEEP, and WAIT. RUN mode is the state where the program is executing, and HOLD mode is the state where program execution is stopped. SLEEP mode and WAIT mode are both program stopped states, but WAIT mode is a state that waits for the completion of specific processing (specified by the program) and switches to RUN mode automatically at the point completion is verified. Of these four modes, HOLD mode can be used for program debugging, and allows the IC internal memory (instruction memory and data memory) to be read and written from external circuits. The IC is started externally by clearing a reset applied with an external pin (the NVRST pin). After startup, the IC can be stopped and restarted with an external pin (the VHOLD pin). The IC operating state can be observed from the VST[2:0] pins. Table 6 lists the processor states as indicated by these pins. Always set the IC to HOLD mode before accessing internal resources when debugging. Operation is not guaranteed if resources are accessed in other modes. Table 6. Internal Operating States VST[2] RUN mode HOLD mode For the RUN to HOLD transition For the SLEEP to HOLD transition For the WAIT to HOLD transition SLEEP mode WAIT mode Low High High High Low Low VST[1] Low Low High Low High Low VST[0] Low Low Low High Low High
8
SDM00008AEM
MN1959041
s Pin Arrangement
16 T NC R NC OUT P TEST7 OUT N TEST6 OUT M TEST3 IN L
15
14 IN
13 IN YD15 IN YD14 IN YD13 GND
12 IN CD10 IN YD17 IN YD16 GND VSS GND VSS
11 IN CD13 IN CD12 IN CD11 GND VSS
10 IN CD16 IN CD15 IN CD14 GND
9 IN NHDI IN NVDI IN CD17 GND
8 OUT
7 OUT
6 OUT LRDO5 OUT LRDO4 OUT LRDO3 2.9 V VDDH
5 OUT LGDO2 OUT LGDO1 OUT LGDO0 2.9 V VDDH 2.9 V
4 OUT LGDO5 OUT LGDO4 OUT LGDO3 2.9 V VDDH 2.9 V
3 OUT LBDO0 OUT LBDO1 OUT LBDO2 OUT
2
1
NC
YD12 IN
CAMCK LRDO2 OUT CIFRQ IN VCKI 2.9 V OUT LRDO1 OUT LRDO0 2.9 V VDDH
NC
NC
NC OUT TEST8 OUT TEST5 OUT TEST2 IN
YD11 IN YD10 OUT
NC OUT LBDO3 OUT
NC OUT LBDO4 OUT VFLG OUT
TEST4 VSSDRAM OUT TEST1 IN GND VSS GND VSS GND VSSDRAM GND VSS GND AVSS GND VSS GND VSS GND VSS GND VSS IN
VSSDRAM VSSDRAM VDDH
LBDO5 LVCKO OUT OUT
NC
NC
NC
NC
NC
NC
VDDH
VDDH NLVSYNCO NLHSYNCO LVVALIDO 2.9 V 2.9 V VDDH 2.9 V VDDH 2.9 V VDDH 3.3 V OUT OUT
TESTMODE3 TESTMODE2 TESTMODE1 IN K TESTMODE0 TESTER IN J NTDRAM PTESTDRAM1 IN H PTESTDRAM0 PSCMR IN G VCOI IN F CFO IN E NPLLRST IN D NYGCMD VTSTMD C VTRWEN B NC A NC NC VST1 NC VST2 OUT VTDI VTDO PLLEN NPLLEN IN OUT VMCK IN VSS IN MINTEST IN VSS GND IN AVDD GND IN VSS 2.9 V IN VSS GND IN GND
NC
NC
NC
NC
NC
NC
NC
NC
VDDH 2.9 V
LHVALIDO NYRESETO OUT PO0 IN/OUT I2CSD IN PI0 IN OUT PO1 IN I2CSCKI IN PI1 IN VA0 IN VA2 IN VA5 IN VA8
NC
NC
NC
NC
NC
NC
NC
NC
VDDH 2.9 V
NC
NC
NC
NC
NC
NC
NC
NC
VDDH 3.3 V
NC
NC
NC
NC
NC
NC
NC
NC
VDDDRAMH VDDDRAMH 3.3 V 1.8 V
NC
NC
NC
NC
NC
NC
NC
NC
VDDDRAMH VDDDRAM NVCS 1.8 V 1.8 V IN VA1 IN VA4 IN VA7 IN VA9
NC GND VSS GND VSS IN
NC
NC
NC
NC
NC
NC
NC 1.8 V
VDDDRAM VDDDRAM 1.8 V VDDDRAM 1.8 V VDD IN VA3 IN VA6 IN VA10 IN VA11
NC GND VSS IN
NC GND VSS
NC GND VSS
NC 1.8 V VDD
NC 1.8 V VDD
NC 1.8 V VDD
VDD 1.8 V VDD
IN/OUT IN/OUT IN/OUT
IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT VPIO3 OUT TEST0 IN VPIO0 VD13 VD10 VD7 VD4 VD1
VTCK NVBTRO NVIRQ0 NVWE1 OUT IN IN IN NVRE IN
NC
IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT VPIO1 VD14 VD11 VD8 VD5 VD2
VHOLD NVIRQ1 OUT VST0 IN
NC
NC
IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT VPIO2 VD15 VD12 VD9 VD6 VD3 VDO NC NC
NVNMI NVRST NVWE0
SDM00008AEM
9
MN1959041
s Pin Descriptions
Pin YDI[7:0] CDI[7:0] NVDI NHDI VCKI CIFRQ CAMCK VFLG I2CSCKI I2CSD LRDO[5:0] LGDO[5:0] LBDO[5:0] NLVSYNCO NLHSYNCO LVVALIDO LHVALIDO LVCKO PI[1:0] PO[1:0] NVRESETO NVCS VA[11:0] VD[15:0] NVWE[1:0] NVRE VPIO[3:0] TEST0 NVIRQ[1:0] NVNMI NVRST NVBTRQ VHOLD VST[2:0] I/O I I I I I O O O I I/O/Z O O O O O O O O I O O I I I/O/Z I I I/O O I I I I I O Misc Host interface Video output Video input Description Luminance data input Color difference input Vertical sync signal Horizontal sync signal Input system video clock (2.250 MHz) CIF size request signal Camera block operating clock (9.000 MHz) MMP1 output frame update flag I2C interface serial clock input I2C interface serial data I/O Red data (Outputs the MMP1 YDO[7:2] bits in V-ASIC through mode.) Green data (Outputs the MMP1 YDO[1:0] and CDO[7:4] bits in V-ASIC through mode.) Blue data (Outputs the MMP1 CDO[3:0] and 2'b00 bits in V-ASIC through mode.) Vertical sync signal Horizontal sync signal Vertical data valid flag Horizontal data valid flag Output system video clock (9.000 MHz) General-purpose input port General-purpose output port Camera vertical sync and horizontal sync output reset signal Chip enable from the MMP-C Input address bus from the MMP-C I/O data bus from the MMP-C Write enable from the MMP-C Read enable from the MMP-C Parallel I/O with the MMP-C Pull Up Pull Up
Normal usage
Contention access signal between the MP and the MMP-C to the HM. NC Maskable interrupt request signal from the MMP-C Nonmaskable interrupt request from the MMP-C MMP-V reset request signal from the MMP-C Boot request at MMP-V reset clear MMP-V hold signal from the MMP-C MMP-V operating state signals to the MMP-C Pull Up Pull Up
10
SDM00008AEM
MN1959041
s Pin Descriptions (continued)
Pin VTCK VTDI VTDO VTRWEN NVGCMD VTSTMD TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 MINTEST TESTER TESTMODE0 TESTMODE1 TESTMODE2 TESTMODE3 PTESTDRAM0 PTESTDRAM1 NTDRAM I/O I/O/Z I/O/Z O I/O/Z I I O O O O O O O O I I I I I I I I I Test mode Debugging interface Description Debugging clock PC value serial output clock (VTCK pin shared function) Serial debugging data input PC value serial output start bit flag (VTDI pin shared function) Serial debugging data output PC value serial output Serial debugging data I/O enable PC value increment flag (VTRWEN pin shared function) MMP-V internal 54 MHz clock gated mode setting TEST pin output mode setting MMP-V internal VIF signal debugging output or PC value [1] output MMP-V internal VIF signal debugging output or PC value [2] output MMP-V internal VIF signal debugging output or PC value [3] output MMP-V internal VIF signal debugging output or PC value [4] output MMP-V internal VIF signal debugging output or PC value [5] output MMP-V internal VIF signal debugging output or PC value [6] output MMP-V internal MIF signal debugging output MMP-V internal MIF signal debugging output Buffer test control input Normal mode/test mode switching Test mode setting Test mode setting Test mode setting Test mode setting DRAM test mode setting 0 DRAM test mode setting 1 Normal mode/shift mode switching during DRAM scan testing Low Low Low NC NC NC NC NC NC NC NC Low Low Low Low Low Low Low Low Low
Normal usage
Low Low
SDM00008AEM
11
MN1959041
s Pin Descriptions (continued)
Pin VMCK NPLLEN PLLEN NPLLRST VCOI AVDD AVSS CFO PSCMR VDDH VDD VSS VDDDRAMH VDDDRAM VSSDRAM PVBBDRAM PVBPDRAM I/O I I I I I I Power supply PLL Description MMP-V operation reference clock (input to the PLL) MMP1 internal operating clock selection Selection of the clock input the MMP1 internal divide-by-two circuit MMP-V internal PLL reset VCO analog voltage input PLL power supply: +2.9 V PLL ground Test pin Test pin Power supply: +2.9 V Power supply: +1.8 V Ground DRAM power supply: +3.3 V DRAM power supply: +1.8 V DRAM ground P detection substrate power supply monitor output P detection test bit line precharge power supply monitor output 2.9 V AVSS High High 2.9 V 1.8 V DGND 3.3 V 1.8 V GND
Normal usage
76.8 KHz Low High High
s Electrical Characteristics
1. Absolute Maximum Ratings at VSS = 0 V Parameter External supply voltage Internal supply voltage Input pin voltage Output pin voltage Output current (Type HL4 pins) Power supply input current Power dissipation Operating temperature Storage temperature
*
Symbol VDD VDDI VI VO IO IV PD Topr Tstg
Rating - 0.3 to +4.6 - 0.3 to +2.5 - 0.3 to VDD + 0.3 (Upper limit: 4.6) - 0.3 to VDD + 0.3 (Upper limit: 4.6) 20 70 (Per pin) 1.77 -20 to +70 -55 to +150
Unit V V V V mA mA mW C C
*
Note) 1. *: When one of VDD and VDDI is off and the other on, through currents flow and the outputs will be undefined. There are no stipulation on the power on and power off sequences. The power supply levels should be applied as close to simultaneously as possible. However, this does no apply when CFO is controlled. 2. Type HL4 pins: CIFRQ, CAMCK, VFLG, I2CSD, LRDO[0] to LRDO[5], LGDO[0] to LGDO[5], LBDO[0] to LBDO[5], NLVSYNCO, NLHSYNCO, LVVALIDO, LHVALIDO, LVCKO, PO[0], PO[1], NVRESRTO, VD[0] to VD[15], VPIO[0] to VPIO[3], VST[0] to VST[2], VTCK, VTDI, VTDO, VTRWEN, TEST[0] to TEST[8] 3. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed. Functional operation is not guaranteed over the complete span of these ranges. 4. All of the VDD and VSS pins must be connected directly to their corresponding power supply and ground levels.
12
SDM00008AEM
MN1959041
s Electrical Characteristics (continued)
2. Recommended Operating Conditions at VSS = 0 V Parameter External supply voltage Internal supply voltage DRAM supply voltage DRAM step-up supply voltage Analog supply voltage Ambient temperature Symbol VDD VDDI VDD18D VDD33D AVDD Ta Conditions Min 2.7 1.65 1.65 3.0 2.7 -20 Typ 2.9 1.8 1.8 3.3 2.9 Max 3.1 1.95 1.95 3.6 3.1 70 Unit V V V V V C
3. I/O Capacitances Parameter Input pins Output pins I/O pins Symbol CIN COUT CIO Conditions VDD = VDDI = VI = 0 V f = 1 MHz, Ta = 25C Min Typ 7 7 7 Max 8 8 8 Unit pF pF pF
4. DC Characteristics at VDD = 2.7 V to 3.1 V, VDDI = 1.65 V to 1.95 V, VSS = 0 V, fTEST = 54 MHz, Ta = -20C to +70C Parameter I/O power supply operating supply current Internal power supply operation supply current DRAM 3.3 V power supply operating supply current (Normal mode) * DRAM 3.3 V power supply operating supply current (Standby test mode) DRAM 3.3 V power supply operating supply current (Dynamaic test mode) DRAM 3.3 V power supply operating supply current (Page mode test mode) DRAM 3.3 V power supply operating supply current (Self refre test mode)
Note) *: Design value
Symbol IDDO
Conditions VI = VDD or VSS , f = 54 MHz, VDD = 2.9 V, VDDI = 1.8 V, outputs open VI = VDD or VSS , f = 54 MHz, VDD = 2.9 V, VDDI = 1.8 V, outputs open VI = VDD or VSS , f = 54 MHz, VDD = 2.9 V, VDDI = 1.8 V, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open VI = VDD or VSS , f = 30 MHz, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open VI = VDD or VSS , f = 30 MHz, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open VI = VDD or VSS , f = 30 MHz, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open VI = VDD or VSS , f = 30 MHz, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open
Min
Typ 4
Max 12.0
Unit mA
IDDIO
50
85.0
mA
IDDDO
0.3
2.0
mA
IDDDO
0.3
4.1
mA
IDDDO
1.3
5.7
mA
IDDDO
0.1
5.0
mA
IDDDO
0.3
4.4
mA
SDM00008AEM
13
MN1959041
s Electrical Characteristics (continued)
4. DC Characteristics at VDD = 2.7 V to 3.1 V, VDDI = 1.65 V to 1.95 V, VSS = 0 V, fTEST = 54 MHz, Ta = -20C to +70C (continued) Parameter DRAM internal power supply operating supply current (Normal mode) * DRAM internal power supply operating supply current (Standby test mode) DRAM internal power supply operating supply current (Dynamaic test mode) DRAM internal power supply operating supply current (Page mode test mode) DRAM internal power supply operating supply current (Self refre test mode) Analog power supply operating supply current Symbol IDDDIO Conditions VI = VDD or VSS , f = 54 MHz, VDD = 2.9 V, VDDI = 1.8 V, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open VI = VDD or VSS , f = 30 MHz, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open VI = VDD or VSS , f = 30 MHz, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open VI = VDD or VSS , f = 30 MHz, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open VI = VDD or VSS , f = 30 MHz, VDDDRAMH = 3.3 V, VDDDRAM = 1.8 V, outputs open VI = VDD or VSS , fin = 76.8 kHz, VDD = 2.9 V, VDDI = 1.8 V, AVDD = 2.9 V, outputs open VI = VDD or VSS , f = 0 MHz, VDD = 2.9 V, VDDI = 1.8 V, AVDD = 2.9 V, outputs open VI = VDD or VSS , fin = 0 kHz, VDD = 2.9 V, VDDI = 1.8 V, AVDD = 2.9 V, outputs open Min Typ 6.0 Max 12.0 Unit mA
IDDDIO
3.0
10.0
mA
IDDDIO
25.0
50.0
mA
IDDDIO
25.0
50.0
mA
IDDDIO
3.0
15.0
mA
IDDAO
0.5
1.0
mA
I/O power supply quiescent supply current
IDDQO
1
20.0
A
Analog power supply quiescent supply current
IDDQAO
1
20.0
A
Note) *: Design value.
14
SDM00008AEM
MN1959041
s Electrical Characteristics (continued)
4. DC Characteristics at VDD = 2.7 V to 3.1 V, VDDI = 1.65 V to 1.95 V, VSS = 0 V, fTEST = 54 MHz, Ta = -20C to +70C (continued) Parameter Symbol Conditions Min Typ Max Unit 1) LVCMOS level inputs: I2CSCKI, PI[0], PI[1], NVCS, VA[0] to VA[11], NVWE[0], NVWE[1], NVRE, NVIRQ[0], NVIRQ[1], NVNMI, NVRST, NVBTRQ, VHOLD, NVGCMD, VTSTMD, TESTER, TESTMODE[0] to TESYMODE[3], PTESTDRAM[0], PTESTDRAM[1], NTDRAM, VMCK, NPLLEN, PLLEN, NPLLRST, CFO, PSCMR High-level input voltage Low-level input voltage Input leakage current VIH VIL ILI VI = VDD or VSS VDD x 0.7 0 VDD VDD x 0.3 10 V V A
2) LVCMOS level inputs with pull-down resistors: YDI[0] to YDI[7], CDI[0] to CDI[7], NVDI, NHDI, VCKI, MINTEST High-level input voltage Low-level input voltage Pull-down resistance Output leakage current VIH VIL RIL ILIL VI = VDD VI = VSS VDD x 0.7 0 10 30 VDD VDD x 0.3 90 10 V V k A
3) LVCMOS level I/O pins: CIFRQ, CAMCK, VFLG, I2CSD, LRDO[0] to LRDO[5], LGDO[0] to LGDO[5], LBDO[0] to LBDO[5], NLVSYNCO, NLHSYNCO, LVVALIDO, LHVALIDO, LVCKO, PO[0], PO[1], NVRESETO, VD[0] to VD[15], VPIO[0] to VPIO[3], VST[0] to VST[2], VTCK, VTDI, VTDO, VTRWEN, TEST[0] to TEST[8] High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current VIH VIL VOH VOL ILO IOH = 4.0 mA, VI = VDD or VSS IOL = 4.0 mA, VI = VDD or VSS VO = High-impedance state, VI = VDD or VSS VD = VDD or VSS FIN = 76.8 kHz, VDD = 2.9 V, VDDI = 1.8 V, AVDD = 2.9 V, R2 = 390 , C1 = 1.0 F, C2 = 0.047 F VDD x 0.7 0 VDD x 0.8 0 VDD VDD x 0.3 VDD VDD x 0.2 10 V V V V A
PLL oscillator frequency
FOSC
53.76
MHz
SDM00008AEM
15
MN1959041
s Electrical Characteristics (continued)
5. AC Characteristics 1) Video input interface timing Parameter Video Input Timing YC data setup time from the VCKI rising edge * YC data hold time from the VCKI rising edge * VCKI low-level period VCKI high-level period VCKI frequency Sync setup time from the VCKI rising edge * Sync hold time from the VCKI rising edge * CAMCK output frequency tVISD tVIHD tVICWVL tVICWVH tVICWV tVISS tVIHS tVICWC VI = VDD or VSS , f = 54 MHz, VDD = 2.9 V, VDDI = 1.8 V 1 5 2 3 12 12 12 12 24 12 12 6 cycle cycle cycle cycle cycle cycle cycle cycle Symbol Conditions Min Typ Max Unit
Note) 1. The stipulated values that follow are all design values. Note that the unit "cycle" in the table refers to one clock period of internal operating frequency. 2. *: This must be used within 1 of the typical value if at all possible.
tVISD YDI[7:0] CDI[7:0] VCKI tVICWVL tVICWV
tVIHD
tVICWVH
Figure 1. YC data input timing tVISS NVDI NHDI VCKI Figure 2. Vsync and Hsync input timing tVICWC CAMCK Figure 3. CAMCK output timing tVIHS
16
SDM00008AEM
MN1959041
s Electrical Characteristics (continued)
5. AC Characteristics (continued) 2) Video output interface timing Parameter Video Output Timing I2CSCKI cycle time I2CSCKI high-level pulse width I2CSCKI low-level pulse width I2CSD setup time I2CSD hold time NLVSYNCO cycle time NLVSYNCO high-level pulse width NLVSYNCO low-level pulse width NLHSYNCO cycle time NLHSYNCO high-level pulse width NLHSYNCO low-level pulse width LVCKO cycle time LVCKO high-level pulse width LVCKO low-level pulse width Delay time from the NLVSYNCO rising edge to the LVVALIDO rising edge LVVALIDO high-level pulse width Delay time from the NLHSYNCO rising edge to the LHVALIDO rising edge LHVALIDO high-level pulse width Delay time from the LHVALIDO falling edge to the point the LVCKO stops Delay time from the LVCKO falling edge to LRDO, LGDO, and LBDO tVOCWI tVOCWIH tVOCWIL tVOSI tVOHI tVOCWV tVOCWVH tVOCWVL tVOCWH tVOCWHH tVOCWHL tVOCWL tVOCWLH tVOCWLL tVODV tVOPWVH tVODH tVOPWHH tVODHC tVODCD VI = VDD or VSS , f = 54 MHz, VDD = 2.9 V, VDDI = 1.8 V 2.5 0.6 1.3 250 300 16.7 16 10 4.0 4.7 16.7 16 16.7 16 s s s ns ns ms ms s s s s ns ns ns ms ms s s s ns Symbol Conditions Min Typ Max Unit
665.7 666.7 667.7 54.6 38.1 15.4 80 40 40 0 12.2 0 55.6 39.1 16.4 111 55 55 12.2 56.6 40.1 17.4 140 70 70 3.78 12.2 19.6
19.54 19.65 19.76 1.67 0 1.78 1.89 9.25
SDM00008AEM
17
MN1959041
s Electrical Characteristics (continued)
5. AC Characteristics (continued) 2) Video output interface timing (continued)
I2CSCKI tVOCWI I2CSD tVOCWIL tVOCWIH
WA WA WA WA WA WA WA WA AC 76543210K D 7 D 6 D 5 D 4 D 3 D 2 D 1 D AC 0K
DA DA DA DA DA DA DA WN AC 6543210 K
Start Condition
Note) DA6 to DA0 : Device Address = 1 000 100 WA7 to WA0 : Word Address = n D : Word Address n Data
Stop Condition
tVOHI tVOSI I2CSCKI I2CSD DA3 DA2 DA1
Figure 4. Random write timing
tVOCWV NLVSYNCO tVOCWVL NLHSYNCO tVODV LVVALIDO tVOPWVH LRDO LGDO LBDO
Black R 1 R 67 R 68 R 218 R 219 R 220 Black
tVOCWVH
Black
G 1
G 67
G 68
G 218
G 219
G 220
Black
Black
B 1
B 67
B 68
B 218
B 219
B 220
Black
12 Lines
1 Line
Displayed Area (220 Lines) 288 Lines
67 Lines
Note) When V_POS = 1, line 0 and lines 221 to 287 will be filled with black in the LCD RGB, and only lines 1 to 220 will be output.
Figure 5. Vertical timing (When V_POS = 1)
18
SDM00008AEM
MN1959041
s Electrical Characteristics (continued)
5. AC Characteristics (continued) 2) Video output interface timing (continued) tVOCWH NLHSYNCO tVOCWHL LHVALIDO tVODH LVCKO tVOCWLL tVOCWLH LRDO LGDO LBDO
Black R 1 R 2 R 3 R 4 R 5 R 6
tVOCWHH
tVOPWHH
tVOCWL
RRRR 173 174 175 176
tVODHC
Black
Black
G 1
G 2
G 3
G 4
G 5
G 6
GGGG 173 174 175 176
Black
Black
B 1
B 2
B 3
B 4
B 5
B 6
BBBB 173 174 175 176
Black
148 Pixels
1 Pixel
Displayed Area (176 Pixels) 352 Pixels
175 Pixels
Note) When H_POS = 1, pixel 0 and pixels 177 to 351 will be filled with black in the LCD RGB, and only pixels 1 to 176 will be output.
tVODCD LVCKO LRDO LGDO LBDO R4/G4/B4 R5/G5/B5 R6/G6/B6 R7/G7/B7
Figure 6. Horizontal timing (When V_POS = 1)
SDM00008AEM
19
MN1959041
s Electrical Characteristics (continued)
5. AC Characteristics (continued) 3) Host interface timing Parameter Symbol Conditions VI = VDD or VSS , f = 54 MHz, VDD = 2.9 V, VDDI = 1.8 V Min Typ Max Unit
Host Memory and Register Access Timing Address and data setup time after NVCS and NVWE[1:0] go low Period that NVCS and NVWE[1:0] are both low Address and data hold time after NVCS and NVWE[1:0] go low Period that NVCS and NVWE[1:0] are both high Address setup time after NVCS and NVRE are both low Period that NVCS and NVRE go low Address hold time after NVCS and NVRE go low Period that NVCS and NVRE are both high Data output delay time after NVCS and NVRE go low Data hold time after NVCS and NVRE go high tHSD 0 cycle
tHCWWL tHHD tHCWWH tHSR tHCWRL tHHA tHCWRH tHDD tHHD
4 0 1 0 5 0 1
5 2 5.5 1.5
4 1
cycle cycle cycle cycle cycle cycle cycle cycle cycle
tHSD VA[11:0] Write address
tHHD
VD[15:0]
Write data
NVCS tHCWWL NVWE[1:0] tHCWWH
NVRE
High
Figure 7. Host memory and register write timing
20
SDM00008AEM
MN1959041
s Electrical Characteristics (continued)
5. AC Characteristics (continued) 3) Host interface timing (continued) tHSA
VA[11:0] Read address tHHA
NVCS
NVWE[1:0]
High tHCWRL tHCWRH
NVRE
VD[15:0]
Hi-Z tHDD
Read data tHHD
Hi-Z
Figure 8. Host memory and register read timing
4) Interrupt input timing Parameter Interrupt Input Timing Low-level setup time after an NVNMI rising edge High-level hold time after an NVNMI rising edge High-level setup time after an NVIRQ falling edge Low-level hold time after an NVIRQ falling edge tISL tIHH tISH tIHL VI = VDD or VSS , f = 54 MHz, VDD = 2.9 V, VDDI = 1.8 V 3 3 3 3 6 6 6 6 cycle cycle cycle cycle Symbol Conditions Min Typ Max Unit
tISL NVNMI
tIHH
Figure 9. NVNMI interrupt input timing
tISH NVIRQ[1:0] tIHL
Figure 10. NVNMI interrupt input timing
SDM00008AEM
21
MN1959041
s Electrical Characteristics (continued)
5. AC Characteristics (continued) 5) Reset and boot timing Parameter Reset and Boot Timing Reset low-level period Boot request high-level setup time after the reset rising edge Boot request high-level hold time after the reset rising edge tCWRS tBSH VI = VDD or VSS , f = 54 MHz, VDD = 2.9 V, VDDI = 1.8 V 6 000 6 000< 3 3< cycle cycle Symbol Conditions Min Typ Max Unit
tBHH
3
3<
cycle
tCWRS NVRST tBSH NVBTRQ tBHH
Figure 11. Reset and boot timing
s Package Dimensions (Units: mm)
* MLGA239-C-1111 (lead free) 11.000.15 8.600.10 (1.20) (1.10)
T R P N M L K J H G F E D C B A
0.850.15 0.05 max.
9.75 0.400.10 0.15 M 0.65
0.6250.2 0.625 0.325
0.2
11.000.15
8.800.10
0.05
1 4-(1.05) 2
3 4
5 6
7
9 11 13 15 8 10 12 14 16
0.325
22
SDM00008AEM
9.75
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

▲Up To Search▲

Price & Availability of MN1959041

	To Download MN1959041 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .